MCP serverio.github.SiliconAnalysts/silicon-analysts

Pure-function chip cost estimator. Given die dimensions (mm), process node, and optional packaging/HBM parameters, returns: estimatedChipCost (USD), dieArea (mm²), grossDiesPerWafe

Heuristic chip manufacturing LEAD TIME estimator (MANUFACTURING CYCLE TIME). Given total mask layers (or a processNode to default them), foundry utilization % (optional — defaults

Fetch one Silicon Analysts record by the id search returned — returns {id, title, text, url, metadata}. text is a compact, citable plain-text rendering of the record's CURRENT valu

Returns 18 AI accelerators (H100/H200/B100/B200/GB200/GB300/Rubin, MI300X/MI355X/MI455X, Gaudi 3, TPU v5p/v6e, Trainium 2/3, Maia 100, MTIA v2) with structured fields: chip, vendor

Historical Benchmarks — the bitemporal benchmark-observations ledger behind the Chip Cost Calculator: wafer cost by node/foundry (deflationary curves), defect-density (D0) learning

Fab Capacity — per-fab, per-tech-node-class capacity from the fabs + fab_capacity_snapshots time-series (100+ fab and advanced-packaging sites: TSMC, Samsung, Intel, SMIC, GlobalFo

Fab Milestones — the dated construction & ramp event log: announcement → groundbreaking → equipment move-in → risk production → HVM, plus expansions and SCHEDULE SLIPS recorded as

Forecast Vintages — third-party forecasts (research firms like TrendForce/WSTS/SEMI, and company capex/bit-growth guidance) archived with their ORIGINAL publication date. Query the

Foundry & advanced-packaging ALLOCATION — the current-state snapshot per node/tech (TSMC/Samsung/Intel/... × N2/N3/CoWoS-L/SoIC/...) plus optional time-series HISTORY. Current fiel

Foundry IR ECONOMICS — per-foundry, per-process-node, per-fiscal-quarter wafer ASP (min/max/blended, USD per 300mm-equivalent wafer, $250-grained) and fab UTILIZATION (%), derived

Returns 10 HBM market sub-tables: accelerators, specs, marketShare, spotPrices (RETIRED 2026-07-28 — frozen), leadingIndicators, qualificationFeed, revenueForecast, supplierRevenue

Sourced HBM qualification tracker: which memory vendor (SK Hynix, Samsung, Micron) passed which AI-accelerator customer's qualification (NVIDIA Vera Rubin/GB300/B300/H200, AMD MI35

Curated market-data TIME SERIES with per-point sourcing — the datasets behind siliconanalysts.com/market-data. Includes: hbm-pricing (HBM contract + blended $/GB by generation, HBM

Market Intelligence — the freshest SOURCED semiconductor market briefs, generated daily from a Tavily + Claude scan of primary press, earnings, and trade outlets. Each brief return

Returns curated supply-chain headlines with trend direction (up/down/neutral), source attribution, and impact analysis. Categories: logic, memory, packaging, connectivity, power, g

Returns two sub-arrays: `packaging` (per-tech cost benchmark + capability matrix for CoWoS-S/L, EMIB, SoIC, InFO-PoP, FC-BGA, FC-CSP, etc.) and `hbmSpecs` (HBM2 through HBM4 cost p

Trade-Policy Timeline — the dated log of semiconductor trade-policy actions (export controls, entity listings, license policies, tariffs, subsidies, retaliation) anchored to GOVERN

"What Changed" — recent MOVEMENTS in Silicon Analysts' public data over a 7d/30d window, derived from the daily snapshot ledger. Each moved metric returns direction (up/down), magn

Forecast Track Record — Silicon Analysts' OWN projections, frozen monthly into write-once vintages and graded against outcomes. Every row: model, scenario (bear/base/bull), series,

Returns 300mm wafer price ranges (min/avg/max USD), defect density, NRE/mask-set cost, and node maturity for: tsmc-n3, tsmc-n5, tsmc-n7, tsmc-n16, tsmc-28, samsung-3nm, samsung-5nm

WFE Order-Book — wafer-fab-equipment maker disclosures (ASML, Applied Materials, Lam Research, KLA, Tokyo Electron) from quarterly IR: bookings, backlog, segment revenue, and guida

Search Silicon Analysts — returns up to 10 matching records as {results: [{id, title, url}]}: curated market datasets and their individual series (HBM contract $/GB by generation,